1. Field of the Invention
The present invention relates to testing an integrated circuit, and more particularly, to an integrated circuit testing method and related circuit utilizing different scan chains at different test stages.
2. Description of the Prior Art
To test faults generated during an integrated circuit manufacturing process, scan chains are generally introduced for testing the integrated circuit. Each scan chain connects two pads and at least one flip-flop in the chip, and the testing time of the scan chain is proportional to a length of the scan chain, where the length of the scan chain indicates a number of the flip-flops on the scan chain. Therefore, the number of the flip-flops on the scan chain needs to be reduced to save testing time.
The number of flip-flops in chips with the same design is fixed, and therefore, to save the testing time, the number of scan chains on a chip is designed to be as many as possible. The more the scan chains implemented, the fewer flip-flops are included in each scan chain.
In a prior art method utilizing scan chains to test the integrated circuit, however, because of the limited number of pins after the chip is packaged, the number of pads in the chip that are available for testing the chip is equal to the number of pins that are available for testing the chip. FIG. 1 is a diagram illustrating prior art functions of the pads in the chip 130 and the pins in the package 100. As shown in FIG. 1, a package 100 comprises a chip 130 and a plurality of pins. These pins comprise: three pins 112 for receiving controlling signals; six pins 114 for receiving test scan-in signals; six pins 116 serving as test scan-out nodes; and an unused pin 118. The chip 130 further comprises: three pads 132 for receiving the controlling signals; six scan-in pads 134 for receiving the scan-in signals; six scan-out pads 136 serving as the test scan-out nodes; and a plurality of unused pads 138.
As shown in FIG. 1, each pin in the package 100 connects to its corresponding pad in the chip 130, and each scan-in pad 134 connects to its corresponding scan-out pad 136 through a plurality of flip-flops in the chip 130 to generate a scan chain. For example, a scan-in pad 134_1 connects to a scan-out pad 136_1 through flip-flops to generate a first scan chain; a scan-in pad 134_2 connects to a scan-out pad 136_2 through flip-flops to generate a second scan chain . . . etc. Therefore, in this prior art package 100, six scan chains are generated.
Generally, a chip could be packaged into several different packages, and the number of scan chains is determined by the package with least pins. Therefore, taking the package 100 shown in FIG. 1 as an exemplary package with the least pins, nine unused pads 138 are wasted and cannot be used to generate the scan chains. Then, on average, each scan chain shown in FIG. 1 must have more flip-flops. Therefore, in the test before the chip is packaged or when the chip is packaged in the package with more pins than the package 100, many pads and pins are wasted, resulting in longer test times.